On the Management of Dynamic Partial Reconfiguration to Speed-up Intrinsic Evolvable Hardware Systems

Turning away from traditional design techniques, which follow the various phases of design and testing, Evolvable Hardware circuits are created through evolutionary strategies aimed at improving the circuits behavior with respect to a given specification. These evolutionary strategies are stochastic search methods that mimic the process of natural biological evolution and are implemented as Evolutionary Algorithms (EAs). This approach permits the exploration of a large design search space, which can ideally enable Evolvable Hardware to find solutions that are more efficient than those found using traditional design methods. This paper describes how an FPGA-based Evolvable Hardware system, using partial dynamic reconfiguration, has been improved introducing a new ICAP controller: the Speed Efficient Dynamic Partial Reconfiguration Controller (SEDPRC). Experimental results have shown that the novel controller brings benefits both to the overall running time (the reconfiguration time has been reduced by 37.2%) and to the resources required to implement the controller itself.